Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device which has satisfactory characteristics is provided. The semiconductor device includes a TFT manufactured by using a satisfactory crystalline semiconductor film and a circuit manufactured by using the TFT. An n-type impurity element (typically, phosphorous) is added to a gettering region of an n-channel TFT. A p-type impurity element (typically, boron) and a rare gas element (typically, argon) are added to a gettering region of a p-channel TFT. Then, there is performed heat treatment for gettering a catalytic element that remains in a semiconductor film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a thin film transistor(hereinafter referred to as TFT) in which a crystalline semiconductorfilm is used for a semiconductor layer, and to a semiconductor device inwhich the TFT is used as a switching element in a driver circuit or apixel portion (particularly, liquid crystal display device). Inparticular, the present invention relates to a TFT and a semiconductordevice, in which a crystalline semiconductor film formed by using acatalytic element that promotes crystallization is used.

[0003] 2. Description of the Related Art

[0004] There have been active studies on a liquid crystal display device(also referred to as liquid crystal panel) in which a TFT is used as aswitching element in a pixel portion, in particular, a liquid crystaldisplay device in which a driver circuit and a pixel portion are formedon the same substrate. The TFT uses a crystalline semiconductor film(typically, a crystalline silicon film) that has high electric fieldeffect mobility and fast movement of carriers to enable high speedoperation, instead of a TFT in which an amorphous semiconductor film(typically, an amorphous silicon film) is used. The above-describedliquid crystal display devices are being sold in actuality.

[0005] A method of irradiating laser light, a thermal crystallizationmethod by heating, a method using a catalytic element, and the like canbe given as methods for manufacturing a crystalline silicon film.

[0006] In the case of using a crystalline semiconductor film formed byusing a catalytic element for a semiconductor layer of a TFT, thecatalytic element used for crystallization of a semiconductor film ismoved to a gettering region from an element region (particularly, achannel forming region) of the TFT in order to improve characteristicsof a semiconductor device. Thus, after an element which has a getteringaction is added to form the gettering region, heat treatment isconducted.

[0007] As gettering processes, there are given and used: a method inwhich an impurity element that imparts one conductivity (n-type) to asemiconductor layer and has a gettering action is added to a sourceregion or a drain region after a crystalline semiconductor film isformed, and heat treatment is conducted to perform activation of theimpurity element and gettering of a catalytic element in the same step;a method in which an impurity element which has a gettering action isadded to a region except an element region of a semiconductor film tosuccessively form a gettering region after a crystalline semiconductorfilm is formed, and heat treatment is conducted to perform gettering ofa catalytic element; and other methods.

[0008] In case of the former method, an n-type impurity element(typically, phosphorous) at high concentration is uniformly added to thegettering region (that later becomes a source region or a drain region)of each of an n-channel TFT and a p-channel TFT. Therefore, the sourceregion or the drain region of the p-channel TFT has to be doped with ap-type impurity element at a concentration twice to three times as highas that of the n-type impurity element in order to reverse n-type top-type. Thus, a process for adding impurities takes a long time, andthere is a problem of throughput. Further, the excessive addition ofions that become acceptors causes a problem of manufacturing cost and aproblem that crystallinity of a semiconductor film is broken and it isdifficult for the semiconductor film to be recrystallized to raise aresistance and lead to reduction of an on current.

[0009] Therefore, the inventors of the present invention performedevaluation on a gettering efficiency of several samples shown in Table 1below in order to find a way of sufficiently gettering a catalyticelement without excessively adding an impurity element to a sourceregion or a drain region that becomes a gettering region in a p-channelTFT. FIGS. 2 to 5 each show a state in which etch pits are observed. InFIGS. 2 to 5 each, the sizes of channel forming regions are 5, 10, 15,20, 30, and 50 μm from the upper portion in the figure. The evaluationis also performed on the size of the channel forming region in whichgettering can be sufficiently performed.

[0010] [Table 1]

[0011] The present inventors selectively remove NiSi_(x) in order tofind the gettering efficiency after the heat treatment for gettering,and the gettering efficiency is evaluated based on the number of holesthat occur after the removal. The hole is called an etch pit. In thecase where the etch pit is not observed in the channel forming region,it is evaluated that the catalytic element that remained in the channelforming region can be moved to the gettering region.

[0012] It is considered that the catalytic element (Ni) is bonded to Sito become NiSi_(x) in a process that the catalytic element moves fromthe channel forming region to the gettering region. A silicon oxide filmis removed with a mixed solution containing 7.13% ammonium bifluoride(NH₄HF₂) and 15.4% ammonium fluoride (NH₄F) (made by Stella ChemifaCorp., trade name: LAL500), and a sample substrate is immersed in anaqueous solution of chemicals mixed with a volume ratio of HF(concentration of 50%): H202 (concentration of 33%): H₂O=45:72:4500(hereinafter referred to as FPM) for 40 minutes, whereby NiSi_(x) can beselectively removed. The holes are generated in the portions whereNiSi_(x) is removed. The holes formed after removing NiSi_(x) can beobserved as black points of the samples in a transmission mode of alight microscope. Note that the black point is referred to as the etchpit in this specification.

[0013] Even a base insulating film (silicon oxide film), which is formedat the substrate side of the silicon film, is removed due to aprocessing time of etching and an aqueous solution of chemicals forprocessing, and thus, the etch pit becomes somewhat larger than theoriginal size of NiSi_(x). However, since precipitated NiSi_(x) isremoved, the etch pit is considered to have substantially the size ofNiSi_(x).

[0014] Here, the present inventors direct their attention to the factthat there is a large difference in the state after etching amongsamples A, B, and D which are judged form that the gettering efficiencyis sufficiently high (the etch pit is not seen even with the size of thechannel forming region of 15 ì m). In the sample B, the etch pit with alarge hole-shape can be observed while in the sample A and the sample D,the etch pit can not be observed. What is seen as a dot shape in thesample D is seemed to be a flaw that is generated on the surface of thesilicon film at the time of adding the impurity element. The presentinventors surmised that it is difficult to occur the precipitation ofNiSi_(x) in the sample A and the sample D, in other words, Ni exists (issolubilized) as an element in silicon lattices. Further, as to thesample D, they considered that a p-type impurity element is added athigh concentration and strong p-type conductivity is imparted, wherebythere is reached the state that boron (B) and nickel (Ni) are easilybonded to each other and NiSix becomes difficult to be generated.Further, NiSi_(x) is easy to precipitate when phosphorous (P) and argon(Ar) exist in the gettering region.

[0015] There has been a problem that an off current suddenly rises in aTFT for which a crystalline semiconductor film formed by using acatalytic element is used. The inventors of the present inventionconsider that NiSi_(x) precipitates in a defect of a semiconductor layerin the crystalline semiconductor film formed by using the catalyticelement, in particular, NiSi_(x) precipitates in a junction portionbetween a channel forming region and a source region or drain region, asa result, off current suddenly rises.

[0016] Then, the present inventors consider that, if only P is added toa gettering region of an n-channel TFT; B and Ar are added to agettering region of a p-channel TFT; and then gettering is performed, acatalytic element (Ni) can be gettered from a region used as an elementin a state that the catalytic element (nickel) singly exists (issolubilized) in silicon lattices with suppressing precipitation ofNiSi_(x).

SUMMARY OF THE INVENTION

[0017] The present invention has been made in view of the above, and hasits object to realize a TFT which has good characteristics by getteringa catalytic element with suppressing precipitation of NiSi_(x) in theentire region that becomes elements to form a high-quality crystallinesemiconductor layer, and manufacturing a TFT using the above-describedcrystalline semiconductor layer.

[0018] Another object of the present invention is to realize asemiconductor device with good characteristics which includes a circuitmanufactured by using the above-described TFT.

[0019] In the present invention, a gettering region (a region to whichphosphorous (P) is added) of a semiconductor layer, which is a regionthat later becomes an n-channel TFT, is not doped with a rare gaselement such as argon (Ar) but with only an n-type impurity element witha gettering action, typically phosphorous (P). A gettering region (aregion to which boron (B) is added) of a region that becomes a p-channelTFT is doped with a rare gas element such as argon (Ar) which has anaction of enhancing a gettering effect, in addition to a p-type impurityelement which has a gettering action, typically boron (B). Then,gettering is performed. Thus, gettering of a catalytic element (nickel)is performed so as not to precipitate NiSi_(x) and so as to obtain asolubilized state that nickel (Ni) exists as an element in a lattice ofsilicon. The gettering of a catalytic element is performed so thatprecipitation of little NiSi_(x) is generated in a source region or adrain region of the semiconductor layer, in particular, in a junctionportion between a channel forming region and the source region or drainregion. Accordingly, the semiconductor device according to the presentinvention is provided. The concentration of the n-type impurity elementin the source region or the drain region of the n-channel TFT is 5×10¹⁹to 5×10²¹/cm³. Further, the concentration of the p-type impurity elementin the source region or the drain region of the p-channel TFT is 1×10¹⁹to 5×10²¹/cm³. Moreover, the concentration of the rare gas element inthe source region or the drain region of the p-channel TFT is 1×10¹⁹ to1×10²²/cm³.

[0020] According to the present invention, the impurity element to beadded to the gettering region is changed in accordance with theconductivity of the TFT, whereby the catalytic element can besufficiently moved to the gettering region from the semiconductor layer(the channel forming region). Thus, the precipitation of NiSi_(x),considered to adversely affect characteristics of the TFT, can besuppressed, and throughput can be improved. Further, a semiconductordevice in which reliability is improved can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In the accompanying drawings:

[0022]FIGS. 1A to 1E show an embodiment mode of the present invention;

[0023]FIG. 2 shows a result of observation of etch pits;

[0024]FIG. 3 shows a result of observation of etch pits;

[0025]FIG. 4 shows a result of observation of etch pits;

[0026]FIG. 5 shows a result of observation of etch pits;

[0027]FIGS. 6A to 6C show an embodiment according to the presentinvention;

[0028]FIGS. 7A to 7C show the embodiment according to the presentinvention;

[0029]FIGS. 8A to 8C show the embodiment according to the presentinvention;

[0030]FIG. 9 shows the embodiment according to the present invention;

[0031]FIGS. 10A to 10C show an embodiment according to the presentinvention;

[0032]FIGS. 11A and 11B show results of measurement of a sheetresistance;

[0033]FIGS. 12A to 12F show examples of electric equipment;

[0034]FIGS. 13A to 13D show examples of electric equipment;

[0035]FIGS. 14A to 14C show examples of electric equipment;

[0036]FIG. 15 shows an embodiment according to the present invention;

[0037]FIGS. 16A to 16D show an embodiment according to the presentinvention; and

[0038]FIGS. 17A to 17C show the embodiment according to the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] An embodiment mode of the present invention will be describedwith reference to FIGS. 1A to 1E. A base insulating film is formed on asubstrate, and an amorphous silicon film is formed on the baseinsulating film. Barium borosilicate glass, alumino borosilicate glass,or quartz can be used for the substrate. On the surface of a substrate10, an inorganic insulating film is formed as a base insulating film 11to have a thickness of 10 to 200 nm. As an example of the baseinsulating film, a silicon oxynitride film manufactured by plasma CVDmay be used. In this embodiment mode, a lamination layer of a 50 nmthick silicon oxynitride film 11 a formed from SiH₄, NH₃, and N₂O and a100 nm thick silicon oxynitride film 11 b formed from SiH₄ and N₂O isused as the base insulating film 11. The base insulating film 11 isformed to prevent alkaline metal contained in a glass substrate fromdiffusing in a semiconductor layer, and thus, this step can be omittedin case of using a quartz substrate. Subsequently, an amorphoussemiconductor film 12 is formed on the base insulating film 11.Typically, silicon or silicon germanium may be used. In this embodimentmode, the amorphous semiconductor film 12 is formed with a thickness of10 to 100 nm by using plasma CVD, low pressure CVD, or sputtering. Inorder to obtain a high-quality crystalline semiconductor film, theconcentration of an impurity element such as oxygen, nitrogen, or carboncontained in the amorphous silicon film 12 needs to be reduced as muchas possible. Therefore, it is desirable that a material gas with highpurity is used or a CVD apparatus dealt in ultra-high vacuum is used.Further, the base insulating film 11 and the amorphous silicon film 12are continuously formed without exposure to the atmosphere, whereby theconcentration of the impurity element can be reduced.

[0040] Subsequently, a metal element which has an action of promotingcrystallization (hereinafter referred to as catalytic element) is addedto the surface of the amorphous silicon film 12. Examples of thecatalytic elements include nickel (Ni), ferrum (Fe), cobalt (Co),ruthenium (Ru), palladium (Pa), osmium (Os), iridium (Ir), platinum(Pt), copper (Cu), and gold (Au). One or a plurality of kinds selectedfrom the group consisting of the above-described elements can be used.Nickel (Ni) is typically used. A catalytic element containing layer 13is formed by applying a nickel acetate salt solution containing 1 to 10ppm nickel by weight with a spinner (spin coating). The catalyticelement containing layer 13 may also be formed by addition with plasmaprocessing, evaporation, or sputtering. In the case where nickel isapplied by spin coating, since the surface of the semiconductor filmsuch as the silicon film is hydrophobic, an ozone containing aqueoussolution is applied to the surface of the amorphous silicon film to forman extremely thin oxide film, the oxide film is etched using a mixedsolution of hydrofluoric acid and hydrogen peroxide solution to form aclean surface, and the surface is processed with the ozone containingaqueous solution again to form an extremely thin oxide film, in order tosatisfactorily make the surface stick to the nickel containing solution.Accordingly, the nickel acetate salt solution can be uniformly applied.

[0041] Next, heat treatment is conducted at 500° C. for 1 hour torelease hydrogen contained in the amorphous silicon film. Then, heattreatment is conducted at 580° C. for 4 hours to form a crystallinesemiconductor film (crystalline silicon film) 14.

[0042] Thereafter, crystalline silicon film 14 may be irradiated withlaser light to repair defects that remain in crystal grains and enhancecrystallinity. Note that excimer laser with a wavelength of 400 nm orless or second harmonic or third harmonic of YAG laser is used for thelaser light. In any case, pulse laser light with a repetition frequencyof about 10 to 1000 Hz is used, the laser light is condensed to 100 to400 mJ/cm² by an optical system, and irradiation of the laser light isperformed to the crystalline semiconductor film with an overlap ratio of90 to 95%.

[0043] The catalytic element at high concentration remains in thecrystalline silicon film 14 obtained by the above step. It has beenrecognized that the catalytic element that remains in the silicon filmprecipitates irregularly, and the precipitation is seen particularly ina grain boundary. Thus, if a TFT element is formed while the catalyticelement remains in the silicon film, the precipitation becomes an escape(leak path) of a faint current, which becomes a cause of sudden increaseof an on current (a current at the time when the TFT is in an offstate). Thus, a problem of fluctuating characteristics arises.Therefore, it is necessary to reduce the concentration of the catalyticelement in the crystalline silicon film, in particular, in a region thatbecomes a channel forming region of the TFT.

[0044] Then, a region to which the catalytic element is moved(hereinafter referred to as gettering region) is formed. A mask 15formed of a silicon oxide film is formed on the crystalline silicon film14. The mask 15 is formed with an opening portion 16 for forming a firstgettering region. An impurity element is added to the exposedcrystalline silicon film through the opening portion 16 to form a firstgettering region 17. Note that the first gettering region 17 is dopedwith an impurity element imparting n-type conductivity (typically,phosphorous).

[0045] Phosphorous (P) is added to the first gettering region 17 by iondoping using phosphine (PH₃) diluted with hydrogen. The concentration ofthe added phosphorous (P) is 5×10¹⁹ to 5×10²¹/cm³, and preferably,5×10¹⁹ to 1×10²¹/cm^(3.)

[0046] Next, a mask 18 formed of a silicon oxide film is formed in orderto form a second gettering region. The mask 18 is formed with an openingportion 19 for forming the second gettering region. An impurity elementis added to the exposed crystalline silicon film through the openingportion 19 to form a second gettering region 20. Note that the secondgettering region 20 is doped with an impurity element imparting p-typeconductivity (typically, boron) and a rare gas element (typically,argon).

[0047] Note that, in addition to argon (Ar), one or a plurality of kindsselected from the group consisting of helium (He), neon (Ne), krypton(Kr), and xenon (Xe) can be used as the rare gas element.

[0048] Boron (B) is added to the second gettering region 20 by iondoping using diborane (B₂H₆) diluted with hydrogen or rare gas. Further,argon (Ar) is added thereto by ion doping. The concentration of theadded boron (B) is 1×10¹⁹ to 5×10²¹/cm³, and preferably, 1×10¹⁹ to5×10²⁰/cm³. The concentration of argon (Ar) is 1×10¹⁹ to 1×10²²/cm³.

[0049] Next, heat treatment for gettering is performed. It is sufficientthat the heat treatment is performed at 450 to 800° C. for 1 minute to24 hours by using any methods such as a heating method with a furnace orRTA (rapid thermal annealing) performed for a very short time. In thisembodiment mode, the heat treatment is performed by jetting gas heatedto 610° C. to the substrate to be processed for 5 minutes, whereby thecatalytic element in the channel forming region is moved to thegettering region. Note that the gettering region may be removed byetching after the gettering step. Further, the conductivity imparted bythe added impurity element differs between the gettering region 17 andthe gettering region 20, and the concentration of the added impurityelement is high. Thus, the gettering region can be used later as thesource region or drain region of the TFT. Note that it can be consideredthat the concentration of the catalytic element is higher in the sourceregion or the drain region used as the gettering region than in thechannel forming region since the catalytic element moves to thegettering region after the heat treatment for gettering.

[0050] The crystalline semiconductor film obtained by using thecatalytic element is the aggregate of crystals with a rod shape orneedle shape, and is satisfactory in that growth is seen with a specificdirectionality when viewed macroscopically.

[0051] Furthermore, the concentration of the catalytic element thatremains in the above-described semiconductor film with satisfactorycrystallinity is sufficiently reduced, whereby characteristics of thesemiconductor device manufactured by using the semiconductor film can beimproved.

[0052] Embodiments

[0053] [Embodiment 1]

[0054] An embodiment of the present invention will be described belowwith reference to FIGS. 6A to 9. Here, a method of simultaneouslymanufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT)in a driver circuit provided in the periphery of the pixel portion onthe same substrate is described in detail.

[0055] In FIG. 6A, a substrate 100 is formed of alumino borosilicateglass. A base insulating film 101 is formed on the substrate 100. Inthis embodiment, a 50 nm thick first silicon oxynitride film 101 a isformed with SiH_(4, NH) ₃, and N₂O as reaction gas, and a 100 nm thicksilicon oxynitride film 101 b is formed with SiH₄ and N₂O as reactiongas, to thereby form a lamination layer.

[0056] Semiconductor layers 103 to 106 (in this embodiment, referred toas a first semiconductor layer 103, a second semiconductor layer 104, athird semiconductor layer 105, and a fourth semiconductor layer 106 forthe sake of convenience) are formed of a semiconductor film 102 with acrystalline structure. After an amorphous semiconductor film is formedon the base insulating film 101, heat treatment is conducted by using acatalytic element (Ni in this embodiment) and jetting an inert gas(here, nitrogen gas) heated to 610° C. to the substrate to be processedfor 5 minutes, to thereby obtain a crystalline semiconductor film.

[0057] After the heat treatment, laser light may be irradiated to thecrystalline semiconductor film in order to enhance the crystallinitymore. The light of an excimer laser with a wavelength of 400 nm or lessor a YAG laser of second harmonic or third harmonic is used for thelaser light. In any case, pulse laser light with a repetition frequencyof about 10 to 1000 Hz is used, the laser light is condensed to 100 to400 mJ/cm² by an optical system, and the laser light is irradiated tothe crystalline semiconductor film with an overlap ratio of 90 to 95%.

[0058] After the crystallization, boron as an acceptor type impurity isadded to the semiconductor film by ion doping in order to control athreshold voltage of a TFT. The concentration of boron added may beappropriately determined by an operator. Note that boron may be added tothe semiconductor film in an amorphous state.

[0059] The thus formed polycrystalline silicon film is divided by anetching process to form the semiconductor layers 103 to 106. A 110 nmthick silicon oxynitride film is formed thereon as a gate insulatingfilm 107 which is formed by plasma CVD using SiH₄ and N₂O (FIG. 6B).

[0060] Further, on the gate insulating film 107, a 30 nm thick tantalumnitride film is formed by sputtering as a first conductive film 108, andfurther, a tungsten film as a second conductive film 109 is formed witha thickness of 300 nm (FIG. 6C).

[0061] Next, as shown in FIG. 7A, a photosensitive resist material isused to form masks 110 to 113. Then, a first etching process isconducted to the first conductive film 108 and the second conductivefilm 109. ICP (inductively coupled plasma) etching is used for etching.Although there is no limitation on an etching gas, CF₄, Cl₂, and O₂ areused for etching the W film and tantalum nitride film. The gas flow rateis set to CF₄: Cl₂:O₂=25:25:10, and RF (13.56 MHz) power of 500 W isapplied to a coil-shape electrode under a pressure of 1 Pa, to therebyperform etching. In this case, RF (13.56 MHz) power of 150 W is appliedalso to the substrate (sample stage) to substantially apply a negativeself-bias voltage. Under the first etching conditions, mainly the W filmis etched to have a predetermined shape.

[0062] Thereafter, the etching gas is changed to CF₄ and Cl₂, the gasflow rate is set to CF₄:Cl₂=30:30, and RF (13.56 MHz) power of 500 W isapplied to the coil-shape electrode under a pressure of 1 Pa to generateplasma and perform etching for about 30 seconds. RF (13.56 MHz) power of20 W is applied also to the substrate (sample stage) to substantiallyapply a negative self-bias voltage. The mixed gas of CF₄ and Cl₂ etchesthe tantalum nitride film and the W film at approximately the same rate.Accordingly, there are formed first shape gate electrodes 114 to 117constituted of first electrodes 114 a to 117 a and second electrodes 114b to 117 b which have a taper end portion. The taper portion is formedat 45° to 75°. In order to perform etching without residue, an etchingtime may be increased by approximately 10 to 20%. The region of the gateinsulating film 107, which is not covered by the first shape gateelectrodes 114 to 117, is etched and thinned by approximately 20 to 50nm.

[0063] Next, as shown in FIG. 7B, a second etching process is conductedwithout removing the masks 110 to 113. CF₄, Cl₂, and O₂ are used asetching gas, the gas flow rate is set to CF₄:Cl₂:O₂=20:20:20, and RF(13.56 MHz) power of 500 W is applied to the coil-shape electrode undera pressure of 1 Pa to generate plasma and perform etching. RF (13.56MHz) power of 20 W is applied also to the substrate (sample stage) toapply a lower self-bias voltage than that in the first etching process.Under the etching conditions, the W film used as the second conductivefilm is subjected to etching. Thus, there are formed second shape gateelectrodes 118 to 121 constituted of third electrodes 118 a to 121 a andfourth electrodes 118 b to 121 b. The region of the gate insulating film107, which is not covered by the second shape gate electrodes 118 to121, is etched and thinned by approximately 20 to 50 nm. Note that thethird electrodes and the fourth electrodes are also referred to aselectrodes (A) and electrodes (B) for the sake of convenience in thisspecification.

[0064] Subsequently, a first doping process is conducted in which animpurity element that imparts n-type conductivity (an n-type impurityelement) is added to the semiconductor layers. The first doping processis performed by ion doping in which ions are injected without masssegregation. In the doping process, the second shape electrodes 118 to121 are used as masks, and a phosphine (PH₃) gas diluted with hydrogenis used to form n-type impurity regions 122 to 125 containing an n-typeimpurity element at a first concentration in the semiconductor films 103to 106. The concentration of phosphorous in the n-type impurity regions122 to 155 is set to 1×10¹⁶ to 1×11¹⁷/cm³.

[0065] Thereafter, first masks 126 and 128 that cover a whole of secondsemiconductor layer 104 and a whole of fourth semiconductor layer 106,respectively, and a second mask 127 that covers a part of the thirdsemiconductor layer 105 and the second shape gate electrode 120 over thethird semiconductor layer 105, are formed. Then, a second doping processis performed. In the second doping process, an n-type impurity region129 containing an n-type impurity element at a second concentration isformed in the first semiconductor layer 103 through the third electrode(electrode (A)) 118 a. The concentration of phosphorous in the n-typeimpurity region 129 is set to 1×10¹⁷ to 1×10¹⁹/cm³.

[0066] Subsequently, a third doping process is performed while the masks126 to 128 remain as they are. An n-type impurity element is added tothe first semiconductor layer 103 and the third semiconductor layer 105through the gate insulating film 107 to form n-type impurity regions 131and 132 containing an n-type impurity element at a third concentration.The concentration of phosphorous in the n-type impurity regions 131 and132 is set to 5×10¹⁹ to 5×10²¹/cm³.

[0067] In this embodiment, the impurity elements are added plural timesas described above. However, the gate insulating film and the thirdelectrodes of gate electrodes are controlled in film thickness or anaccelerating voltage in doping is adjusted, whereby the n-type impurityregions containing an n-type impurity element at the secondconcentration and the n-type impurity regions containing an n-typeimpurity element at the third concentration can be formedsimultaneously.

[0068] Next, as shown in FIG. 8A, masks 133 and 134 that cover the firstsemiconductor layer 103 and the third semiconductor layer 105,respectively, are formed, and then, a fourth doping process isconducted. In the doping process, diborane (B₂H₆) gas diluted withhydrogen or diborane gas diluted with rare gas is used, and a p-typeimpurity region 136 containing a p-type impurity element at a firstconcentration and a p-type impurity region 135 containing a p-typeimpurity element at a second concentration are formed in the secondsemiconductor layer 104. Further, in the fourth semiconductor layer 106for a storage capacitor in the pixel portion, a p-type impurity region138 containing a p-type impurity element at the first concentration anda p-type impurity region 137 containing a p-type impurity element at thesecond concentration are formed. The p-type impurity regions 136 and 138are formed to overlap the electrodes (A) 119 a and 121 a, respectively,and are doped with boron in a concentration range of 1×10 ¹⁸ to1×10²⁰/cm³. The p-type impurity regions 135 and 137 are doped with boronin a concentration range of 1×10¹⁹ to 5×10²¹/cm³, preferably, 1×10¹⁹ to5×10²⁰/cm³.

[0069] In this embodiment, the addition of the p-type impurity element(boron) is performed after the addition of the n-type impurity element(phosphorous) at a high concentration (5×10¹⁹ to 5×10²¹/cm³). However,it may be possible that the region that becomes the n-channel TFT iscovered with a mask, the addition of the p-type impurity element (thefourth doping process in this embodiment) is conducted, and then, theaddition of the n-type impurity element at the high concentration (thesecond doping process and the third doping process in this embodiment)is conducted.

[0070] Next, a rare gas element (Ar in this embodiment) is added whilethe masks 133 and 134 remain as they are. The crystalline structure ofthe semiconductor layer to which the rare gas element is added is brokento be amorphous. Note that the rare gas element exists without beingcoupled with silicon. The crystalline structure is broken as describedabove, whereby there is obtained the state that it is easy for thecatalytic element to move to a gettering region from a channel formingregion.

[0071] Through the above-described processes, the regions, to whichphosphorous, or boron and argon are added, are formed in the respectivesemiconductor films. The second shape gate electrodes 118 to 120 becomegate electrodes. Further, the second shape electrode 121 becomes one ofcapacitor electrodes of the storage capacitor in the pixel portion.

[0072] Next, as shown in FIG. 8B, heat treatment is performed in aheated inert gas atmosphere in order to activate the impurity elementsadded to the respective semiconductor films. In this embodiment, heattreatment is conducted for 5 minutes in a nitrogen gas heated to 610° C.In the heat treatment, there is also performed a process of moving thecatalytic element used in the crystallization process of thesemiconductor films to the gettering region (the source region or drainregion of the n-channel TFT doped with phosphorous at highconcentration, and the source region or drain region of the p-channelTFT doped with boron and argon at high concentration) from the channelforming regions of the TFTs.

[0073] The element which has a gettering action and is added to thegettering region of the n-channel TFT is only phosphorous (P), and it isdifficult for NiSi_(x) to be precipitated. Thus, gettering can besufficiently performed. Further, the elements which has a getteringaction and are added to the gettering region of the p-channel TFT areboron (B) and argon (Ar), and argon (Ar) compensates for the getteringefficiency of boron (B). Thus, gettering can be sufficiently performed.Therefore, by the above-described heat treatment, the catalytic elementis moved to the gettering region, and the concentration of the catalyticelement (Ni) that remains in the channel forming region can be reducedto 1×10¹⁷/cm³ or less, preferably, 1×10¹⁶/cm³ or less. Although then-type impurity element is added to the gettering region of thep-channel TFT at a concentration of 1×10¹⁶ to 1×10¹⁷/cm³, thisconcentration does not have the gettering action. Thus, the n-typeimpurity element does not adversely affect the gettering region of thep-channel TFT.

[0074] Thereafter, as shown in FIG. 8B, a first interlayer insulatingfilm 139, which is formed of a silicon nitride film or a siliconoxynitride film, is formed to have a thickness of 50 nm by using plasmaCVD. Then, heat treatment is conducted at 410° C. by using a clean ovento thereby perform hydrogenation of the semiconductor layers withhydrogen released from the silicon nitride film or the siliconoxynitride film.

[0075] Next, a second interlayer insulating film 140 is formed fromacrylic on the first interlayer insulating film 139. Then, contact holesare formed. In this etching process, the first interlayer insulatingfilm and the second interlayer insulating film in an external inputterminal portion is formed are removed. Then, wirings 142 to 149 areformed by laminating a titanium film and an aluminum film.

[0076] Through the above steps, there can be formed on the samesubstrate a driver circuit 205 which has an n-channel TFT 201 and ap-channel TFT 202 and a pixel portion 206 which has a pixel TFT 203 anda storage capacitor 204. The storage capacitor 204 is constituted of thesemiconductor layer 106, the gate insulating film 107, and the capacitorwiring 121.

[0077] The n-channel TFT 201 of the driver circuit 205 includes achannel forming region 150, the n-type impurity region 129 (L_(ov)region) containing an n-type impurity element at the secondconcentration and overlapping the electrode (A) 118 a of the gateelectrode, and the n-type impurity region 131 containing an n-typeimpurity element at the third concentration which functions as thesource region or drain region. The length of the L_(ov) region in achannel length direction is 0.5 to 2.5 μm, preferably, 1.5 μm. Theabove-described structure of the L_(ov) region is taken for preventingdeterioration of the TFT mainly due to a hot carrier effect. Then-channel TFT and the p-channel TFT can constitute a shift resistercircuit, a buffer circuit, a level shifter circuit, a latch circuit, andthe like. Particularly, the structure of the n-channel TFT 201 issuitable for the buffer circuit in which a driving voltage is high forthe purpose of preventing the deterioration due to the hot carriereffect.

[0078] The p-channel TFT 202 of the driver circuit 205 includes achannel forming region 151, the p-type impurity region 135 (the regionthat functions as the source region or drain region) containing a p-typeimpurity element at the second concentration outside of the electrode(A) 119 a of the gate electrode, and the p-type impurity region 136containing a p-type impurity element at the first concentration andoverlapping the electrode (A) 119 a.

[0079] The TFT (pixel TFT) 203 of the pixel portion 206 includes achannel forming region 152, the n-type impurity region 124 containing ann-type impurity element at the first concentration outside the electrode(A) 120 a of the gate electrode, and the n-type impurity region 132containing an n-type impurity element at the third concentration whichfunctions as the source region or drain region. Further, the p-typeimpurity regions 137 and 138 are formed in the semiconductor layer 106that functions as one of the electrodes of the storage capacitor 204.

[0080] As described above, in the present invention, arrangement can beappropriately determined in accordance with circuits that differ inoperation conditions, for example, the driver circuit portion and thepixel portion.

[0081]FIG. 9 is a circuit diagram showing an example of a circuitstructure of an active matrix substrate. A pixel portion 601 formed bybeing incorporated with TFTs, a data signal line driver circuit 602, andscanning signal line driver circuits 606 and 607 are formed.

[0082] The data signal line driver circuit 602 is composed of a shiftresister 603, latches 604 and 605, a buffer circuit, and the like. Aclock signal and a start signal are input to the shift register 603, anda digital data signal and a latch signal are input the latches. Further,the scanning signal line driver circuit 606 is also composed of a shiftresister, a buffer circuit, and the like. Although the number of pixelsin the pixel portion 601 is arbitrary, 1024×768 pixels are provided inXGA.

[0083] A display device with active matrix drive can be formed by usingthe above-described active matrix substrate. When this embodiment isapplied to a liquid crystal display device and the pixel electrode isformed from a light reflective material, a reflection type displaydevice can be formed. A liquid crystal display device or a lightemitting device in which a pixel portion is constituted of organic lightemitting elements can be formed by using the above-described activematrix substrate. Accordingly, the active matrix substrate that isadapted for the reflection type display device can be manufactured.

[0084] [Embodiment 2]

[0085] In this embodiment, another embodiment of a method ofmanufacturing a semiconductor device will be described with reference toFIGS. 10A to 10C. Note that the processes until the first etchingprocess shown in FIG. 7A in accordance with Embodiment 1 are the same inthis embodiment. FIG. 10A shows the state of the substrate on which theelement that has undergone the processes until the first etching processshown in FIG. 7A is formed.

[0086] In FIG. 10A, there are provided the substrate 100, the baseinsulating film 101 (the base insulating film 101 a formed of a siliconoxynitride film, and the base insulating film 101 b formed of a siliconoxynitride film), the first to fourth semiconductor layers 103 to 106,the gate insulating film 107, and the first shape gate electrodes 114 to117.

[0087] Here, a first doping process is conducted. The first to fourthsemiconductor layers 103 to 106 are doped with an n-type impurityelement to thereby form n-type impurity regions 301 to 304 containing afirst concentration n-type impurity element at a low concentration of1×10¹⁵ to 1×10¹⁷/cm³.

[0088] Next, a second etching process is performed. The first shape gateelectrodes 114 to 117 (constituted of the first electrodes 114 a to 117a and the second electrodes 114 b to 117 b) are etched to form secondshape gate electrodes 305 to 308 (electrodes (A) 305 a to 308 a andelectrodes (B) 305 b to 308 b).

[0089] After the processes until this point are completed, themanufacturing process proceeds from the second doping process shown inFIG. 7C in Embodiment 1. As a result, the active matrix substrate shownin FIG. 8C can be manufactured.

[0090] [Embodiment 3]

[0091] In accordance with this embodiment, it is possible to apply thepresent invention to a manufacturing process of a bottom gate type TFT.The manufacturing process of a bottom gate type TFT will be describedwith reference to FIGS. 16A to 17C.

[0092] An insulating film such as a silicon oxide film, a siliconnitride film, or a silicon oxynitride film is formed (not shown) on asubstrate 50, and a conductive film is formed in order to form a gateelectrode. The conductive film is patterned to have a desired shape andform a gate electrode 51. As the conductive film, a conductive film,which is comprised of one element selected from the group consisting ofTa, Ti, W, Mo, Cr, and Al or contains one element selected from thegroup as its main constituent, may be used.

[0093] Next, a gate insulating film 52 is formed. The gate insulatingfilm may be comprised of a single layer of a silicon oxide film, asilicon nitride film, or a silicon oxynitride film, or a laminationlayer of any of the above films.

[0094] Subsequently, an amorphous silicon film 53 as an amorphoussemiconductor film is formed with a thickness of 10 to 150 nm by thermalCVD, plasma CVD, low pressure CVD, evaporation, or sputtering. Since thegate insulating film 52 and the amorphous silicon film 53 can be formedby the same film deposition method, both the films may be continuouslyformed. With the continuous formation, there is no exposure to anatmosphere, and the contamination of the film surface can be prevented.Thus, variation of characteristics of the TFT to be manufactured andfluctuation of the threshold voltage can be reduced.

[0095] Then, a catalytic element that promotes crystallization isapplied to the amorphous silicon film 53 to form a catalytic elementcontaining layer 54. Thereafter, heat treatment is performed to form acrystalline silicon film.

[0096] After the crystallization process, there is formed a 100 to 400nm thick insulating film 55 that protects the crystalline silicon film(a channel forming region) in the later process of adding impurities.

[0097] Next, using a mask formed of resist, an impurity element thatimparts n-type conductivity is added to the crystalline silicon filmthat later becomes an active layer of an n-channel TFT at aconcentration of 5×10¹⁹ to 5×10²¹/cm³, preferably, 1×10²⁰ to 1×10²¹ /cm³To the crystalline silicon film that later becomes an active layer of ap-channel TFT, a p-type impurity element is added at a concentration of1×10¹⁹ to 5×10²¹/cm³, preferably, 1×10²⁰ to 5×10²¹/cm³, and a rare gaselement is added at a concentration of 1×10¹⁹ to 1×10²²/cm³. As aresult, a source region, a drain region, and an LDD region are formed.

[0098] Next, an activation process of the impurity elements added to thecrystalline silicon film is performed. Capture (gettering) of thecatalytic element applied to the silicon film in the crystallizationprocess is also performed simultaneously with the activation. By theheat treatment, the catalytic element is moved to gettering regions thatare: a region to which the n-type impurity element is added at highconcentration; and a region to which the p-type impurity element and therare gas element are added at high concentration.

[0099] Subsequently, the insulating film on the crystalline silicon filmis removed, the crystalline silicon film is patterned to have a desiredshape, and then, an interlayer insulating film 56 is formed. Theinterlayer insulating film is formed of an insulating film such as asilicon oxide film, a silicon nitride film, or a silicon oxynitride filmto have a thickness of 500 to 1500 nm.

[0100] Thereafter, contact holes that reach the source regions and drainregions of the respective TFTs are formed, and wirings 57 forelectrically connecting the respective TFTs are formed.

[0101] As described above, the present invention can be applied and usedto TFTs with any shape.

[0102] [Embodiment 4]

[0103] In this embodiment, a process of manufacturing an active matrixliquid crystal display device from the active matrix substratemanufactured in accordance with any of Embodiments 1 to 3 will bedescribed.

[0104] First, the active matrix substrate in the state of FIG. 8C ismanufactured in accordance with Embodiment 1. Then, as shown in FIG. 15,an orientation film 180 is formed on the active matrix substrate, and arubbing process is performed.

[0105] Next, a counter substrate 181 is prepared, and colored layers 182and 183 and a leveling film 184 are formed on the counter substrate 181.The red colored layer 182 and the blue colored layer 183 are partiallyoverlapped with each other to thereby be made to function as a lightshielding film. Although not shown in FIG. 15, there exists a regionwhere the red colored layer and a green colored layer are overlappedwith each other to be made to function as a light shielding film.

[0106] Next, a counter electrode 185 is formed in the pixel portion.Then, an orientation film 186 is entirely formed, and a rubbing processis performed.

[0107] Subsequently, the active matrix substrate on which the pixelportion and the driver circuit are formed and the counter substrate onwhich the colored layers and the counter electrode are formed are bondedto each other by using a sealing material 187. The sealing material 187is mixed with a filler. The two substrates can be bonded to each otherwith a uniform interval by using the filler and a columnar spacer.Thereafter, a liquid crystal material 188 is injected between the bondedsubstrates, and a sealant (not shown) seals completely. A known liquidcrystal material may be used as the liquid crystal material 188. In thisway, the active matrix liquid crystal display device shown in FIG. 15 iscompleted.

[0108] [Embodiment 5]

[0109]FIGS. 11A and 11B show results of measuring a sheet resistance ofa sample to which gettering is conducted in accordance with the presentinvention.

[0110] In order to compare argon addition concentration dependency ofthe sheet resistance, the measurement is carried out on samples 1 to 4among which the argon addition concentration is varied with a constantconcentration of an n-type impurity element (phosphorous), and samples 5to 7 among which the argon addition concentration is varied with aconstant concentration of a p-type impurity element (boron). Thedetailed impurity concentrations of the measured samples are shown inTable 2.

[0111] [Table 2]

[0112] Note that FIGS. 11A and 11B show the results of measuring thesheet resistance of the samples 1 to 7 shown in Table 2 after 5-minuteheat treatment at any temperature of 570° C., 610° C., 650° C., or 690°C.

[0113] Regarding the samples 1 to 4 to which phosphorous (P) is added,the lowest sheet resistance can be obtained in the sample 1 according tothe present invention, to which argon (Ar) is not added.

[0114] Further, as to the samples 5 to 8 to which boron (B) is added,the sheet resistance does not rise so much even when both boron (B) andargon (Ar) are added.

[0115] Accordingly, the semiconductor film with satisfactorycrystallinity can be formed by using the catalytic element when thepresent invention is applied. Further, the catalytic element can besufficiently gettered without generation of NiSi_(x) in thesemiconductor layer. Thus, a satisfactory semiconductor device can berealized without deterioration of the sheet resistance due to theimpurity element added to the source region or drain region that becomesthe gettering region.

[0116] [Embodiment 6]

[0117] A CMOS circuit and a pixel portion formed in accordance with thepresent invention can be used for an active matrix display (a liquidcrystal display device). In other words, the present invention can beapplied to all electronic equipments incorporating the liquid crystaldisplay device with the display portion.

[0118] As the electronic equipment, a video camera, a digital camera, aprojector (rear or front type), a head mounted display (goggle typedisplay), a personal computer, a portable information terminal (mobilecomputer, cellular phone, electronic book, etc.), and the like can beenumerated. Examples of these are shown in FIGS. 12, 13 and 14.

[0119]FIG. 12(A) shows a personal computer including a main body 2001,an image input portion 2002, a display portion 2003, and a keyboard2004, etc.

[0120]FIG. 12(B) shows a video camera including a main body 2101, adisplay portion 2102, an audio input portion 2103, an operation switch2104, a battery 2105, and an image receiving portion 2106, etc.

[0121]FIG. 12(C) shows a mobile computer including a main body 2201, acamera portion 2202, an image receiving portion 2203, an operationswitch 2204, and a display portion 2205, etc.

[0122]FIG. 12(D) shows a goggle type display including a main body 2301,a display portion 2302, and an arm portion 2303, etc.

[0123]FIG. 12(E) shows a player using a recording medium records aprogram (hereinafter referred to as a “recording medium”), including amain body 2401, a display portion 2402, a speaker portion 2403, arecording medium 2404, and an operation switch 2405, etc. This deviceuses a DVD (Digital Versatile Disc), CD, or the like for the recordingmedium, and can perform music appreciation, film appreciation, games andthe use for Internet.

[0124]FIG. 12(F) shows a digital camera including a main body 2501, adisplay portion 2502, a viewfinder 2503, an operation switch 2504, andan image receiving portion (not shown), etc.

[0125]FIG. 13(A) shows a front type projector including a projectiondevice 2601 and a screen 2602, etc.

[0126]FIG. 13(B) shows a rear type projector including a main body 2701,a projection device 2702, a mirror 2703, and a screen 2704, etc.

[0127]FIG. 13(C) is a view showing a structure of the projection device2601,2702 in FIG. 13(A) and FIG. 13(B). The projection device 2601,2702includes a light-source optical system 2801, mirrors 2802, 2804-2806, adichroic mirror 2803, a prism 2807, a liquid crystal display device2808, a phase difference plate 2809 and a projection optical system2810. The projection optical system 2810 includes an optical systemcontaining a projection lens. Although the embodiment showed an exampleof three-plate type, the invention is not especially limited thereto,For example, it may be a single-plate type. Meanwhile, the practitionermay properly provide an optical system, such as an optical lens, a filmhaving a polarization property, a film for adjusting a phase difference,IR film or the like, in an optical path shown at the arrow in FIG.13(C).

[0128]FIG. 13(D) is a view showing an example of a structure of thelight-source optical system 2801 in FIG. 13(C). In the embodiment, thelight-source optical system 2801 includes a reflector 2811, a lightsource 2812, a lens array 2813, 2814, a polarization converter 2815 anda focus lens 2816. Incidentally, the light-source optical system shownin FIG. 13D is one example and the invention is not limited thereto. Forexample, the practitioner may provide an optical system, such as anoptical lens, a film having a polarization property, a film foradjusting a phase difference, IR film or the like, in the opticalsystem.

[0129] However, according to the projectors shown in FIG. 13, there isshown a case of using a transmission type electro-optical device and anexample of applying a reflection type electro-optical device is notillustrated.

[0130]FIG. 14(A) shows a cellular phone including a display panel 3001and an operation panel 3002. The display panel 3001 and the operationpanel 3002 are connected to each other in a connection portion 3003. Inthe connection portion 3003, the angle θ of a face, which is provided adisplay portion 3004 of the display panel 3001, and a face, which isprovided an operation key 3006 of the operation panel 3002, can bechanged arbitrary.

[0131]FIG. 14(B) shows a portable book (electronic book) including amain body 3101, a display portion 3102, 3103, a recording medium, anoperation switch, and an antennal, etc.

[0132]FIG. 14(C) shows a display including a main body 3201, a supportbase 3202, and a display portion 3203, etc. The display according to theinvention is advantageous particularly in the case of large screenformation and is advantageous in the display having a diagonal length of10 inch or more (particularly, 30 inch or more).

[0133] As described above, the applicable range of the present inventionis extremely wide, and the invention can be applied to electronicequipments in all fields.

[0134] The n-type impurity element is added to the gettering region ofthe n-channel TFT, the p-type impurity element and the rare gas elementare added to the gettering region of the p-channel TFT, and then theheat treatment is performed, whereby the catalytic element (Ni) thatremains in the semiconductor layer can be gettered without precipitationof NiSi_(x). By applying the present invention, the TFT with highreliability can be manufactured.

[0135] Further, when the present invention is applied, the highconcentration of n-type impurity element is not added to the sourceregion or the drain region of the p-channel TFT. Thus, it is possible tosuppress the added amount (concentration) of the p-type impurityelement, which was excessively added in a conventional case in order toreverse the n-type, to the necessary and minimum level, and thus,throughput is improved. Further, since the impurity elements are notexcessively added, the crystallinity is not broken so much, andrecrystallization is satisfactory realized. As a result, the resistanceof the source region or the drain region does not rise. Accordingly, thereduction of the on current can also be improved. TABLE 1 Added ElementP B Ar After Gettering Sample A ◯ X X Gettering Efficiency: ◯ EtchPit:No Sample B ◯ X ◯ Gettering Efficiency: ◯ EtchPit: Large Sample C X ◯ XGettering Efficiency: Δ EtchPit: Large Sample D X ◯ ◯ GetteringEfficiency: ◯ EtchPit: No

[0136] TABLE 2 sample Argon (Ar) Concentration (/cm³) phosphorous (P)Concentration: 8.2 × 10¹⁹ /cm³ Treatment Temperature: 570° C., 610° C.,650° C., 690° C. Treatment Time: 5 min. Sample 1 — Sample 2 3.3 ×10¹⁹/cm³ Sample 3 6.5 × 10¹⁹/cm³ Sample 4 1.3 × 10²⁰/cm³ Boron (B)Concentration: 2.1 × 10²⁰/cm³ Treatment Temperature: 570° C., 610° C.,650° C., 690° C. TreatmentTime: 5 min. Sample 5 — Sample 6 6.5 ×10¹⁹/cm³ Sample 7 1.3 × 10²⁰/cm³

What is claimed is:
 1. A semiconductor device comprising an n-channelTFT and a p-channel TFT over the same substrate, wherein each of then-channel TFT and the p-channel TFT comprises a semiconductor layercomprising at least a channel forming region, a source region, and adrain region, and wherein at least one of the source region and thedrain region of the p-channel TFT comprises a p-type impurity elementand a rare gas element.
 2. A semiconductor device comprising ann-channel TFT and a p-channel TFT over the same substrate, wherein eachof the n-channel TFT and the p-channel TFT comprises a semiconductorlayer comprising at least a channel forming region, a source region, anda drain region, wherein at least one of the source region and the drainregion of the n-channel TFT comprises a n-type impurity element, andwherein at least one of the source region and the drain region of thep-channel TFT comprises a p-type impurity element and a rare gaselement.
 3. A semiconductor device according to claim 1, wherein thesemiconductor layer comprises a low concentration impurity region.
 4. Asemiconductor device according to claim 2, wherein the semiconductorlayer comprises a low concentration impurity region.
 5. A semiconductordevice according to claim 1, wherein each of the n-channel TFT and thep-channel TFT comprises the a gate insulating film on the semiconductorlayer and a gate electrode on the gate insulating film.
 6. Asemiconductor device according to claim 2, wherein each of the n-channelTFT and the p-channel TFT comprises the a gate insulating film on thesemiconductor layer and a gate electrode on the gate insulating film. 7.A semiconductor device comprising an n-channel TFT and a p-channel TFTover the same substrate, wherein each of the n-channel TFT and thep-channel TFT comprises: a gate electrode over the substrate; a gateinsulating film on the gate electrode; and a semiconductor layer on thegate insulating film, wherein the semiconductor layer comprises achannel forming region, a source region, and a drain region, and whereinat least one of the source region and the drain region of the p-channelTFT comprises a p-type impurity element and a rare gas element.
 8. Asemiconductor device comprising an n-channel TFT and a p-channel TFTover the same substrate, wherein each of the n-channel TFT and thep-channel TFT comprises: a gate electrode over the substrate; a gateinsulating film on the gate electrode; and a semiconductor layer on thegate insulating film, wherein the semiconductor layer comprises achannel forming region, a source region, and a drain region, wherein atleast one of the source region and the drain region of the n-channel TFTcomprises a n-type impurity element, and wherein at least one of thesource region and the drain region of the p-channel TFT comprises ap-type impurity element and a rare gas element.
 9. A semiconductordevice comprising a first n-channel TFT, a p-channel TFT, and a secondn-channel TFT formed in a pixel portion over the same substrate, whereinthe first n-channel TFT comprises: a first semiconductor layercomprising a channel forming region, a source region, a drain region,and a first impurity region containing a first concentration of n-typeimpurity element; a gate insulating film on the semiconductor layer; anda gate electrode on the gate insulating film, wherein the gate electrodecomprises a lamination layer of a first conductive film and a secondconductive film, wherein a part of the first conductive film overlapsthe first impurity region through the gate insulating film, wherein thep-channel TFT comprises: a second semiconductor layer comprising achannel forming region, a source region, a drain region, and a lowconcentration impurity region; a gate insulating film on thesemiconductor layer; and a gate electrode on the gate insulating film,wherein the second n-channel TFT formed in the pixel portion comprises:a third semiconductor layer comprising: a channel forming region, asource region, a drain region, and a second impurity region containing asecond concentration of n-type impurity element; a gate insulating filmon the semiconductor layer; and a gate electrode on the gate insulatingfilm, wherein at least one of the source region and the drain region ineach of the first n-channel TFT and the second n-channel TFT comprisesan n-type impurity element, and wherein at least one of the sourceregion and the drain region of the p-channel TFT comprises a p-typeimpurity element and a rare gas element.
 10. A semiconductor deviceaccording to claim 1, wherein the semiconductor layer comprises acatalytic element that promotes crystallization of an amorphous siliconfilm.
 11. A semiconductor device according to claim 2, wherein thesemiconductor layer comprises a catalytic element that promotescrystallization of an amorphous silicon film.
 12. A semiconductor deviceaccording to claim 7, wherein the semiconductor layer comprises acatalytic element that promotes crystallization of an amorphous siliconfilm.
 13. A semiconductor device according to claim 8, wherein thesemiconductor layer comprises a catalytic element that promotescrystallization of an amorphous silicon film.
 14. A semiconductor deviceaccording to claim 9, wherein the semiconductor layer comprises acatalytic element that promotes crystallization of an amorphous siliconfilm.
 15. A semiconductor device according to claim 10, wherein aconcentration of the catalytic element in the source region or the drainregion is higher than in the channel forming region.
 16. A semiconductordevice according to claim 11, wherein a concentration of the catalyticelement in the source region or the drain region is higher than in thechannel forming region.
 17. A semiconductor device according to claim12, wherein a concentration of the catalytic element in the sourceregion or the drain region is higher than in the channel forming region.18. A semiconductor device according to claim 13, wherein aconcentration of the catalytic element in the source region or the drainregion is higher than in the channel forming region.
 19. A semiconductordevice according to claim 14, wherein a concentration of the catalyticelement in the source region or the drain region is higher than in thechannel forming region.
 20. A semiconductor device according to claim 2,wherein a concentration of an n-type impurity element in the sourceregion or the drain region of the n-channel TFT is 5×10¹⁹ to 5×10²¹/cm³.21. A semiconductor device according to claim 8, wherein a concentrationof an n-type impurity element in the source region or the drain regionof the n-channel TFT is 5×10¹⁹ to 5×10²¹/cm³.
 22. A semiconductor deviceaccording to claim 9, wherein a concentration of an n-type impurityelement in the source region or the drain region of the n-channel TFT is5×10¹⁹ to 5×10²¹/cm³.
 23. A semiconductor device according to claim 1,wherein a concentration of the p-type impurity element in the sourceregion or the drain region of the p-channel TFT is 1×10¹⁹ to 5×10²¹/cm³.24. A semiconductor device according to claim 2, wherein a concentrationof the p-type impurity element in the source region or the drain regionof the p-channel TFT is 1×10¹⁹ to 5×10²¹/cm³.
 25. A semiconductor deviceaccording to claim 7, wherein a concentration of the p-type impurityelement in the source region or the drain region of the p-channel TFT is1×10¹⁹ to 5×10²¹/cm³.
 26. A semiconductor device according to claim 8,wherein a concentration of the p-type impurity element in the sourceregion or the drain region of the p-channel TFT is 1×10¹⁹ to 5×10²¹/cm³.27. A semiconductor device according to claim 9, wherein a concentrationof the p-type impurity element in the source region or the drain regionof the p-channel TFT is 1×10¹⁹ to 5×10²¹/cm³.
 28. A semiconductor deviceaccording to claim 1, wherein a concentration of the rare gas element inthe source region or the drain region of the p-channel TFT is 1×10¹⁹ to1×10²²/cm³.
 29. A semiconductor device according to claim 2, wherein aconcentration of the rare gas element in the source region or the drainregion of the p-channel TFT is 1×10¹⁹ to 1×10²²/cm³.
 30. A semiconductordevice according to claim 7, wherein a concentration of the rare gaselement in the source region or the drain region of the p-channel TFT is1×10¹⁹ to 1×10²²/cm³.
 31. A semiconductor device according to claim 8,wherein a concentration of the rare gas element in the source region orthe drain region of the p-channel TFT is 1×10¹⁹ to 1×10²²/cm³.
 32. Asemiconductor device according to claim 9, wherein a concentration ofthe rare gas element in the source region or the drain region of thep-channel TFT is 1×10¹⁹ to 1×10²²/cm³.
 33. A semiconductor deviceaccording to claim 2, wherein the n-type impurity element is an elementthat belongs to group 15 of the periodic table.
 34. A semiconductordevice according to claim 8, wherein the n-type impurity element is anelement that belongs to group 15 of the periodic table.
 35. Asemiconductor device according to claim 9, wherein the n-type impurityelement is an element that belongs to group 15 of the periodic table.36. A semiconductor device according to claim 1, wherein the p-typeimpurity element is an element that belongs to group 13 of the periodictable.
 37. A semiconductor device according to claim 2, wherein thep-type impurity element is an element that belongs to group 13 of theperiodic table.
 38. A semiconductor device according to claim 7, whereinthe p-type impurity element is an element that belongs to group 13 ofthe periodic table.
 39. A semiconductor device according to claim 8,wherein the p-type impurity element is an element that belongs to group13 of the periodic table.
 40. A semiconductor device according to claim9, wherein the p-type impurity element is an element that belongs togroup 13 of the periodic table.
 41. A semiconductor device according toclaim 1, wherein the rare gas element is one or a plurality of kindsselected from the group consisting of argon (Ar), helium (He), neon(Ne), krypton (Kr), and xenon (Xe).
 42. A semiconductor device accordingto claim 2, wherein the rare gas element is one or a plurality of kindsselected from the group consisting of argon (Ar), helium (He), neon(Ne), krypton (Kr), and xenon (Xe).
 43. A semiconductor device accordingto claim 7, wherein the rare gas element is one or a plurality of kindsselected from the group consisting of argon (Ar), helium (He), neon(Ne), krypton (Kr), and xenon (Xe).
 44. A semiconductor device accordingto claim 8, wherein the rare gas element is one or a plurality of kindsselected from the group consisting of argon (Ar), helium (He), neon(Ne), krypton (Kr), and xenon (Xe).
 45. A semiconductor device accordingto claim 9, wherein the rare gas element is one or a plurality of kindsselected from the group consisting of argon (Ar), helium (He), neon(Ne), krypton (Kr), and xenon (Xe).
 46. A semiconductor devicecomprising an n-channel TFT and a p-channel TFT over the same substrate,wherein each of the n-channel TFT and the p-channel TFT comprises asemiconductor layer comprising at least a channel forming region, asource region, and a drain region, wherein the semiconductor layercomprises a catalytic element that promotes crystallization of anamorphous silicon film, and wherein the catalytic element exists in asolubilized state between silicon lattices in the semiconductor layer.47. A semiconductor device according to claim 46, wherein thesemiconductor layer comprises a low concentration impurity region.
 48. Asemiconductor device according to claim 46, wherein each of then-channel TFT and the p-channel TFT comprises the a gate insulating filmon the semiconductor layer and a gate electrode on the gate insulatingfilm.
 49. A semiconductor device comprising an n-channel TFT and ap-channel TFT over the same substrate, wherein each of the n-channel TFTand the p-channel TFT comprises: a gate electrode over a substrate, agate insulating film on the gate electrode, and a semiconductor layer onthe gate insulating film, wherein the semiconductor layer comprises achannel forming region, a source region, and a drain region, wherein thesemiconductor layer comprises a catalytic element that promotescrystallization of an amorphous silicon film, and wherein the catalyticelement exists in a solubilized state between silicon lattices in thesemiconductor layer.
 50. A semiconductor device comprising a firstn-channel TFT, a p-channel TFT, and a second n-channel TFT formed in apixel portion over the same substrate, wherein the first n-channel TFTcomprises: a first semiconductor layer comprising a channel formingregion, a source region, a drain region, and a first impurity regioncontaining a first concentration of n-type impurity element; a gateinsulating film on the semiconductor layer; and a gate electrode on thegate insulating film, wherein the gate electrode comprises a laminationlayer of a first conductive film and a second conductive film, wherein apart of the first conductive film overlaps the first impurity regionthrough the gate insulating film, wherein the p-channel TFT comprises: asecond semiconductor layer comprising a channel forming region, a sourceregion, a drain region, and a low concentration impurity region; a gateinsulating film on the semiconductor layer; and a gate electrode on thegate insulating film, wherein the second n-channel TFT formed in thepixel portion comprises: a third semiconductor layer comprising: achannel forming region, a source region, a drain region, and a secondimpurity region containing a second concentration of n-type impurityelement; a gate insulating film on the semiconductor layer; and a gateelectrode on the gate insulating film, wherein each of the first,second, and third semiconductor layers comprises a catalytic elementthat promotes crystallization of an amorphous silicon film, and whereinthe catalytic element exists in a solubilized state between siliconlattices in the semiconductor layer.
 51. A semiconductor deviceaccording to claim 46, wherein an etch pit is not generated in thesource region and in the drain region in the semiconductor layer fromthe result of an etching test with an FPM solution.
 52. A semiconductordevice according to claim 49, wherein an etch pit is not generated inthe source region and in the drain region in the semiconductor layerfrom the result of an etching test with an FPM solution.
 53. Asemiconductor device according to claim 50, wherein an etch pit is notgenerated in the source region and in the drain region in thesemiconductor layer from the result of an etching test with an FPMsolution.
 54. A semiconductor device according to claim 51, wherein theetching test with the FPM solution employs the FPM solution containinghydrofluoric acid at a concentration of 0.5% and hydrogen peroxide at aconcentration of 0.5% and is performed for 30 to 60 minutes at a liquidtemperature of 15 to 30° C.
 55. A semiconductor device according toclaim 52, wherein the etching test with the FPM solution employs the FPMsolution containing hydrofluoric acid at a concentration of 0.5% andhydrogen peroxide at a concentration of 0.5% and is performed for 30 to60 minutes at a liquid temperature of 15 to 30° C.
 56. A semiconductordevice according to claim 53, wherein the etching test with the FPMsolution employs the FPM solution containing hydrofluoric acid at aconcentration of 0.5% and hydrogen peroxide at a concentration of 0.5%and is performed for 30 to 60 minutes at a liquid temperature of 15 to30° C.
 57. A semiconductor device according to claim 46, wherein aconcentration of the catalytic element in the semiconductor layer ishigher in the source region or in the drain region than in the channelforming region.
 58. A semiconductor device according to claim 49,wherein a concentration of the catalytic element in the semiconductorlayer is higher in the source region or in the drain region than in thechannel forming region.
 59. A semiconductor device according to claim50, wherein a concentration of the catalytic element in thesemiconductor layer is higher in the source region or in the drainregion than in the channel forming region.
 60. A semiconductor deviceaccording to claim 1, wherein the catalytic element is one or aplurality of kinds selected from the group consisting of nickel (Ni),ferrum (Fe), cobalt (Co), ruthenium (Ru), palladium (Pa), osmium (Os),iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).
 61. Asemiconductor device according to claim 2, wherein the catalytic elementis one or a plurality of kinds selected from the group consisting ofnickel (Ni), ferrum (Fe), cobalt (Co), ruthenium (Ru), palladium (Pa),osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).62. A semiconductor device according to claim 7, wherein the catalyticelement is one or a plurality of kinds selected from the groupconsisting of nickel (Ni), ferrum (Fe), cobalt (Co), ruthenium (Ru),palladium (Pa), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu),and gold (Au).
 63. A semiconductor device according to claim 8, whereinthe catalytic element is one or a plurality of kinds selected from thegroup consisting of nickel (Ni), ferrum (Fe), cobalt (Co), ruthenium(Ru), palladium (Pa), osmium (Os), iridium (Ir), platinum (Pt), copper(Cu), and gold (Au).
 64. A semiconductor device according to claim 9,wherein the catalytic element is one or a plurality of kinds selectedfrom the group consisting of nickel (Ni), ferrum (Fe), cobalt (Co),ruthenium (Ru), palladium (Pa), osmium (Os), iridium (Ir), platinum(Pt), copper (Cu), and gold (Au).
 65. A semiconductor device accordingto claim 46, wherein the catalytic element is one or a plurality ofkinds selected from the group consisting of nickel (Ni), ferrum (Fe),cobalt (Co), ruthenium (Ru), palladium (Pa), osmium (Os), iridium (Ir),platinum (Pt), copper (Cu), and gold (Au).
 66. A semiconductor deviceaccording to claim 49, wherein the catalytic element is one or aplurality of kinds selected from the group consisting of nickel (Ni),ferrum (Fe), cobalt (Co), ruthenium (Ru), palladium (Pa), osmium (Os),iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).
 67. Asemiconductor device according to claim 50, wherein the catalyticelement is one or a plurality of kinds selected from the groupconsisting of nickel (Ni), ferrum (Fe), cobalt (Co), ruthenium (Ru),palladium (Pa), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu),and gold (Au).
 68. A method of manufacturing a semiconductor device,comprising the steps of: forming an amorphous semiconductor film on aninsulating film; adding a catalytic element to the amorphoussemiconductor film; conducting heat treatment to form a crystallinesemiconductor film; forming a first mask with a first opening portion onthe crystalline semiconductor film and adding an n-type impurity elementto a region that becomes a source region or a drain region of ann-channel TFT; forming a second mask with a second opening portion onthe crystalline semiconductor film and adding a p-type impurity elementand a rare gas element to a region that becomes a source region or adrain region of a p-channel TFT; and conducting heat treatment.
 69. Amethod of manufacturing a semiconductor device according to claim 68,wherein the method comprises the step of forming the second mask withthe second opening portion on the crystalline semiconductor film andadding the p-type impurity element and the rare gas element to theregion that becomes the source region or the drain region of thep-channel TFT after the step of forming the first mask with the firstopening portion on the crystalline semiconductor film and adding then-type impurity element to the region that becomes the source region orthe drain region of the n-channel TFT.
 70. A method of manufacturing asemiconductor device, comprising: forming an amorphous semiconductorfilm on an insulating film; adding a catalytic element to the amorphoussemiconductor film; conducting heat treatment to form a crystallinesemiconductor film; forming a first mask with a first opening portion onthe crystalline semiconductor film and adding an n-type impurity elementto a region that becomes a source region or a drain region of ann-channel TFT; forming a second mask with a second opening portion onthe crystalline semiconductor film and adding a p-type impurity elementand a rare gas element to a region that becomes a source region or adrain region of a p-channel TFT; and conducting heat treatment foractivating the n-type and p-type impurity elements and gettering thecatalytic element.
 71. A method of manufacturing a semiconductor deviceaccording to claim 70, wherein the method comprises the step of formingthe second mask with the second opening portion on the crystallinesemiconductor film and adding the p-type impurity element and the raregas element to the region that becomes the source region or the drainregion of the p-channel TFT after the step of forming the first maskwith the first opening portion on the crystalline semiconductor film andadding the n-type impurity element to the region that becomes the sourceregion or the drain region of the n-channel TFT.
 72. A method ofmanufacturing a semiconductor device, comprising: forming an amorphoussemiconductor film on an insulating film; adding a catalytic element tothe amorphous semiconductor film; conducting heat treatment in a heatedinert gas atmosphere form a crystalline semiconductor film; forming afirst mask with a first opening portion on the crystalline semiconductorfilm and adding an n-type impurity element to a region that becomes asource region or a drain region of an n-channel TFT; forming a secondmask with a second opening portion on the crystalline semiconductor filmand adding a p-type impurity element and a rare gas element to a regionthat becomes a source region or a drain region of a p-channel TFT; andconducting heat treatment for activating the n-type and p-type impurityelements and gettering the catalytic element.
 73. A method ofmanufacturing a semiconductor device according to claim 72, wherein themethod comprises the step of forming the second mask with the secondopening portion on the crystalline semiconductor film and adding thep-type impurity element and the rare gas element to the region thatbecomes the source region or the drain region of the p-channel TFT afterthe step of forming the first mask with the first opening portion on thecrystalline semiconductor film and adding the n-type impurity element tothe region that becomes the source region or the drain region of then-channel TFT.
 74. A method of manufacturing a semiconductor device,comprising: forming an amorphous semiconductor film on an insulatingfilm; adding a catalytic element to the amorphous semiconductor film;conducting heat treatment in a heated inert gas atmosphere form acrystalline semiconductor film; forming a first mask with a firstopening portion on the crystalline semiconductor film and adding ann-type impurity element at a concentration of 5×10¹⁹ to 5×10²¹/cm³ to aregion that becomes a source region or a drain region of an n-channelTFT; forming a second mask with a second opening portion on thecrystalline semiconductor film and adding a p-type impurity element at aconcentration of 1×10¹⁹ to 5×10²¹/cm³ and a rare gas element at aconcentration of 1×10¹⁹ to 1×10²²/cm³ to a region that becomes a sourceregion or a drain region of a p-channel TFT; and conducting heattreatment in a heated inert gas atmosphere for activating the n-type andp-type impurity elements and gettering the catalytic element.
 75. Amethod of manufacturing a semiconductor according to claim 74, whereinthe method comprises the step of forming the second mask with the secondopening portion on the crystalline semiconductor film and adding thep-type impurity element at the concentration of 1×10¹⁹ to 5×10²¹/cm³ andthe rare gas element at the concentration of 1×10¹⁹ to 1×10²²/cm³ to theregion that becomes the source region or the drain region of thep-channel TFT after the step of forming the first mask with the firstopening portion on the crystalline semiconductor film and adding then-type impurity element at the concentration of 5×10¹⁹ to 5×10²¹/cm³ tothe region that becomes the source region or the drain region of then-channel TFT.
 76. A method of manufacturing a semiconductor device,comprising: forming an amorphous semiconductor film on an insulatingfilm; adding a catalytic element to the amorphous semiconductor film;conducting heat treatment in a heated inert gas atmosphere to form acrystalline semiconductor layer; forming a gate insulating film on thesemiconductor layer; forming a first conductive film on the gateinsulating film and a second conductive film on the first conductivefilm; etching the first conductive film and the second conductive filmto form a first conductive layer; adding an n-type impurity element at aconcentration of 1×10¹⁶ to 1×10¹⁸ /cm³ to the semiconductor layer;etching the first conductive layer to form a second conductive layer;covering a region that becomes a p-channel TFT with a first mask andadding an n-type impurity element at a concentration of 5×10¹⁹ to5×10²¹/cm³ to a region that becomes an n-channel TFT; covering theregion that becomes the n-channel TFT with a second mask and adding ap-type impurity element at a concentration of 1×10¹⁹ to 5×10²¹/cm³ and arare gas element at a concentration of 1×10¹⁹ to 1×10²²/cm³ to theregion that becomes the p-channel TFT; and conducting heat treatment ina heated inert gas atmosphere for activating the n-type and p-typeimpurity elements and gettering the catalytic element.
 77. A method ofmanufacturing a semiconductor device according to claim 76, wherein themethod comprises the step of covering the region that becomes then-channel TFT with the second mask and adding the p-type impurityelement at the concentration of 1×10¹⁹ to 5×10²¹/cm³ and the rare gaselement at the concentration of 1×10¹⁹ to 1×10²²/cm³ to the region thatbecomes the p-channel TFT after the step of covering the region thatbecomes the p-channel TFT with the first mask and adding the n-typeimpurity element at the concentration of 5×10¹⁹ to 5×10²¹/cm³ to theregion that becomes the n-channel TFT.
 78. A method of manufacturing asemiconductor device according to claim 76, wherein the method comprisesthe step of forming a first interlayer insulating film on the secondconductive layer before the step of conducting the heat treatment in theheated inert gas atmosphere.
 79. A method of manufacturing asemiconductor device, comprising: forming a gate electrode over aninsulating surface; forming a gate insulating film on the gateelectrode; forming a semiconductor film on the gate insulating film;adding a catalytic element to the semiconductor film and then conductingheat treatment for forming a crystalline semiconductor film; forming aprotective film comprising an insulating film on the crystallinesemiconductor film; adding an n-type impurity element at a concentrationof 5×10¹⁹ to 5×10²¹/cm³ to a region that becomes a source region or adrain region of an n-channel TFT; adding a p-type impurity element at aconcentration of 1×10¹⁹ to 5×10²¹/cm³ and a rare gas element at aconcentration of 1×10¹⁹ to 1×10²²/cm³ to a region that becomes a sourceregion or a drain region of a p-channel TFT; and conducting heattreatment for activating the n-type and p-type impurity elements andgettering the catalytic element.
 80. A method of manufacturing asemiconductor device according to claim 79, wherein the method comprisesthe step of adding the p-type impurity element at the concentration of1×10¹⁹ to 5×10²¹/cm³ and the rare gas element at the concentration of1×10¹⁹ to 1×10²²/cm³ to the region that becomes the source region or thedrain region of the p-channel TFT after the step of adding the n-typeimpurity element at the concentration of 5×10¹⁹ to 5×10²¹/cm³ to theregion that becomes the source region or the drain region of then-channel TFT.
 81. A method of manufacturing a semiconductor deviceaccording to claim 68, wherein the n-type impurity element is an elementthat belongs to group 15 of the periodic table.
 82. A method ofmanufacturing a semiconductor device according to claim 70, wherein then-type impurity element is an element that belongs to group 15 of theperiodic table.
 83. A method of manufacturing a semiconductor deviceaccording to claim 72, wherein the n-type impurity element is an elementthat belongs to group 15 of the periodic table.
 84. A method ofmanufacturing a semiconductor device according to claim 74, wherein then-type impurity element is an element that belongs to group 15 of theperiodic table.
 85. A method of manufacturing a semiconductor deviceaccording to claim 76, wherein the n-type impurity element is an elementthat belongs to group 15 of the periodic table.
 86. A method ofmanufacturing a semiconductor device according to claim 79, wherein then-type impurity element is an element that belongs to group 15 of theperiodic table.
 87. A method of manufacturing a semiconductor deviceaccording to claim 68, wherein the p-type impurity element is an elementthat belongs to group 13 of the periodic table.
 88. A method ofmanufacturing a semiconductor device according to claim 70, wherein thep-type impurity element is an element that belongs to group 13 of theperiodic table.
 89. A method of manufacturing a semiconductor deviceaccording to claim 72, wherein the p-type impurity element is an elementthat belongs to group 13 of the periodic table.
 90. A method ofmanufacturing a semiconductor device according to claim 74, wherein thep-type impurity element is an element that belongs to group 13 of theperiodic table.
 91. A method of manufacturing a semiconductor deviceaccording to claim 76, wherein the p-type impurity element is an elementthat belongs to group 13 of the periodic table.
 92. A method ofmanufacturing a semiconductor device according to claim 79, wherein thep-type impurity element is an element that belongs to group 13 of theperiodic table.
 93. A method of manufacturing a semiconductor deviceaccording to claim 68, wherein the rare gas element is one or aplurality of kinds selected from the group consisting of argon (Ar),helium (He), neon (Ne), krypton (Kr), and xenon (Xe).
 94. A method ofmanufacturing a semiconductor device according to claim 70, wherein therare gas element is one or a plurality of kinds selected from the groupconsisting of argon (Ar), helium (He), neon (Ne), krypton (Kr), andxenon (Xe).
 95. A method of manufacturing a semiconductor deviceaccording to claim 72, wherein the rare gas element is one or aplurality of kinds selected from the group consisting of argon (Ar),helium (He), neon (Ne), krypton (Kr), and xenon (Xe).
 96. A method ofmanufacturing a semiconductor device according to claim 74, wherein therare gas element is one or a plurality of kinds selected from the groupconsisting of argon (Ar), helium (He), neon (Ne), krypton (Kr), andxenon (Xe).
 97. A method of manufacturing a semiconductor deviceaccording to claim 76, wherein the rare gas element is one or aplurality of kinds selected from the group consisting of argon (Ar),helium (He), neon (Ne), krypton (Kr), and xenon (Xe).
 98. A method ofmanufacturing a semiconductor device according to claim 79, wherein therare gas element is one or a plurality of kinds selected from the groupconsisting of argon (Ar), helium (He), neon (Ne), krypton (Kr), andxenon (Xe).
 99. A method of manufacturing a semiconductor deviceaccording to claim 68, wherein the catalytic element is one or aplurality of kinds selected from the group consisting of nickel (Ni),ferrum (Fe), cobalt (Co), ruthenium (Ru), palladium (Pa), osmium (Os),iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).
 100. A methodof manufacturing a semiconductor device according to claim 70, whereinthe catalytic element is one or a plurality of kinds selected from thegroup consisting of nickel (Ni), ferrum (Fe), cobalt (Co), ruthenium(Ru), palladium (Pa), osmium (Os), iridium (Ir), platinum (Pt), copper(Cu), and gold (Au).
 101. A method of manufacturing a semiconductordevice according to claim 72, wherein the catalytic element is one or aplurality of kinds selected from the group consisting of nickel (Ni),ferrum (Fe), cobalt (Co), ruthenium (Ru), palladium (Pa), osmium (Os),iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).
 102. A methodof manufacturing a semiconductor device according to claim 74, whereinthe catalytic element is one or a plurality of kinds selected from thegroup consisting of nickel (Ni), ferrum (Fe), cobalt (Co), ruthenium(Ru), palladium (Pa), osmium (Os), iridium (Ir), platinum (Pt), copper(Cu), and gold (Au).
 103. A method of manufacturing a semiconductordevice according to claim 76, wherein the catalytic element is one or aplurality of kinds selected from the group consisting of nickel (Ni),ferrum (Fe), cobalt (Co), ruthenium (Ru), palladium (Pa), osmium (Os),iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).
 104. A methodof manufacturing a semiconductor device according to claim 79, whereinthe catalytic element is one or a plurality of kinds selected from thegroup consisting of nickel (Ni), ferrum (Fe), cobalt (Co), ruthenium(Ru), palladium (Pa), osmium (Os), iridium (Ir), platinum (Pt), copper(Cu), and gold (Au).